Best Paper Award
Design of a Novel p-GaN gate AlGaN/GaN/InGaN HEMT and Its Application in Boost Converter
Pei-Jung Wang1*, Chia-Yu Hsieh1 and Yue-Ming Hsin2
1Interdisciplinary Program of Electrical Engineering & Computer Science, National Central University, Taiwan, 2Department of Electrical Engineering, National Central University, Taiwan
A novel p-GaN gate AlGaN/GaN/InGaN high electron mobility transistor (HEMT) is demonstrated in this work. The proposed new structure applies the conventional p-GaN gate structure and adds an InGaN interlayer. The study includes the design of the new device, the simulation and fitting of I-V characteristics using Silvaco TCAD, and the comparison of device characteristics between the conventional p-GaN gate structure and the new structure. The new device exhibits a high ID,MAX of 478 mA/mm, and a relatively low ON-resistance of 8 Ωmm while maintaining the same VTH = 2.54 V. Applying the new transistor to a 1 kW boost converter, the power consumption is reduced by 33.43%, and the peak efficiency improves to 96.5%.
Study of the Cryogenic Effects on BSIM Parameters of Mobility and Subthreshold Swing
Yu-Che Liu1*, De-Xiang Jair1, Yun-Chung Cheng1, Yu-Ting Chuang2, Chih-Ho Tu2, Hann-Huei Tsai2 and Meng-Hsueh Chiang1
1MS program on Nano-Integrated Circuit Engineering, Department of Electrical Engineering National Cheng Kung University, Taiwan, 2National Applied Research Laboratories, Taiwan Semiconductor Research Institute, Taiwan
This work mainly uses MOSFET devices manufactured with 40nm CMOS process and uses the parameter extraction software UTMOST IV to apply the BSIM bulk VerilogA model to extract the parameters of subthreshold swing and mobility. Finally, we can focus on the relationships of the parameters at 300K, 200K, 77K, and 4K. So that we will understand how physical properties at low temperatures affect each parameter.
Addressing the actual process issues using TCAD simulations for metal-oxide-semiconductor field-effect transistors
Yu-Gan Wang1, Ya-Chi Huang1, Chub-Yi Yeh1, Jia-Wei Chen1*, Meng-Hsueh Chiang1, Yu-Sheng Lai 2, and Cheng Ming Huang2
1Department of Electrical Engineering, National Cheng Kung University, Taiwan, 2Taiwan Semiconductor Research Institute, Taiwan
With the advancement of Moore’s Law, size reduction is a major challenge in today’s integrated circuit industry. As the size continues to shrink, the short channel effects have become more and more significant, and will cause the characteristics of the transistors to be unpredictable, such as gate-induced drain leakage, high subthreshold swing, etc., and the simulation and actual manufacturing processes encounter more challenges. There are many unexpected problems. This paper mainly discusses the electrical difference between the complementary metal-oxide semiconductor from the TCAD software simulation process and the semiconductor process provided by Taiwan Semiconductor Research Institute, and provides solutions to address practical issues in the actual process.
High performance ultraviolet photodetector based on Mg-IGZO thin film transistor with a patterned Ni0.47Mg0.53O capping layer
Yu-Hao Chen1, Lu-Tang Wang1, Rong-Ming Ko2*, Chien-Hung Wu3, and Shui-Jinn Wang1,2*
1Institute of Microelectronics, Dept. of Electrical Engineering, National Cheng Kung University, Taiwan, 2Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng Kung University, Taiwan, 3Department of Optoelectronics and Materials Engineering, Chung Hua University, Taiwan
The use of Mg-IGZO channel layer and patterned NixMg1-xO capping layer (CL) to improve the sensing performance of TFT ultraviolet photodetectors (UV-PDs) is demonstrated. Experimental results show that Mg (3.17%)-IGZO TFT has improved electrical properties with a higher Ion/Ioff of 2.13×107, a lower SS of 138 mV/dec, and μFE of 26.8 cm2/V-s. The effects of the channel thickness and Ni0.47Mg0.53OCL on the optoelectrical properties of devices are also investigated. Among the fabricated devices, 45-nm-thick Mg (3.17%)-IGZO TFT with a patterned Ni0.47Mg0.53OCL exhibits the best UV detection performance with photoresponsivity of 1390 A/W and a detectivity of 1.19 × 1016 Jones at 275 nm. It attributed to Ni0.47Mg0.53O/Mg-IGZO pn HJ formed on the back channel to suppress the dark current, and provide a significant amount of photogenerated electrons to increase the photo current during UV irradiation
Design consideration and Optimization of high voltage vertical β-Ga2O3 Schottky barrier diodes with trench staircase field plate
Wei-Ting Ting1, Chao-Hsin Wu1,2,3*
1Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taiwan, 2Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 3Graduate School of Advanced Technology, National Taiwan University, Taiwan
Gallium oxide (Ga2O3) based vertical Schottky barrier diodes have considerable potential to develop high voltage and high speed switching applications. However, due to the lack of p-type doping in Ga2O3, some edge termination techniques are hard to be applied, making field plate structures available and critical ways to enhance the breakdown voltage. The study presents vertical β-Ga2O3 SBDs with a staircase field plate on a deep trench filled with various dielectrics. Theoretical two dimensional simulations have been performed using the ATLAS device simulator from Silvaco to investigate and analyze the influence of the different insulators under the field plate. And by virtue of the superior breakdown properties of the trench staircase field plate structure, it exhibits great capacity for high power applications. Furthermore, the appropriate dielectric for the aforementioned structure is also examined and determined.
Less Power and Less Read Disturbed Coupling MIS(p) Memory
Chi-Yi Kao* and Jenn-Gwo Hwu
Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
Utilize charge coupling mechanism, a less read disturbed memory device was proposed in this work. Al2O3/SiO2 stack was chosen as dielectric layers to storage injecting charges. This device showed large memory window and 100 s retention time. With regard to power consumption, one cycle of operation consumed only 76 nW, which is a potential candidate for low power operating.
Highly Stacked Ge0.75Si0.25 Nanosheet nFETs
Shee-Jier Chueh1, Yi-Chun Liu1, Chun-Yi Cheng1, Bo-Wei Huang1, Chien-Te Tu1, and Chee-Wee Liu1,2*
1Graduate Institute of Electronics Engineering, and 2Graduate School of Advanced Technology, National Taiwan University, Taiwan.
The 8 stacked Ge0.75Si0.25 nanosheets with high inter-channel uniformity are demonstrated by the co-optimization of CVD epitaxy and isotropic wet etching. With the sophisticated epitaxy of 18 layers, involving a Ge buffer, 9 heavily P-doped Ge sacrificial layers (SLs), and 8 Ge0.75Si0.25 channels, isotropic H2O2 wet etching without high energy ion damage is used to fabricate this highly stacked nanosheets device. Remarkable inter-channel uniformity is achieved thanks to the superior etching selectivity of n+Ge SLs over undoped Ge0.75Si0.25 channels. The ION of 36μA per stack (390μA/μm per channel footprint) at VOV = VDS = 0.5V is obtained. The tensile strain of Ge0.75Si0.25 nanosheets with microbridge structure is improved to 1.7%, simulated by ANSYS.
Atomic-Layer-Deposited In2O3 Channel Ferroelectric Field Effect Transistor using RuO2/Hf0.5Zr0.5O2 Gate Stack
Yan-Kui Liang1,2, Yu Chen1, Li-Chi Peng1, Sheng‐Chi Hung1, Tsung-Te Chou2, Chi-Chung Kei2, Sheng-Shiuan Yeh1, Edward-Yi Chang1, and Chun-Hsiung Lin1*
1International College of Semiconductor Technology, National Yang Ming Chiao Tung University, Taiwan, 2Taiwan Instrument Research Institute, National Applied Research Laboratories, Taiwan.
In this work, we demonstrate the back-end-of-line (BEOL) compatible FeFETs with In2O3 and Hf0.5Zr0.5O2 (HZO) as channel and ferroelectric gate insulator by atomic layer deposition (ALD). High memory performance is achieved, exhibiting a wide memory window of 3.1 V in a DC sweep of just ± 4V. These results indicate that oxide semiconductor FeFET with RuO2 gate electrode is a promising candidate toward monolithic 3D integration for memory application.
van der Waals Epitaxy of 2D Material Hetero-structures for Interconnect Applications
Che-Jia Chang1,2, Po-Cheng Tsai1, Tzu-Hsuan Chang1, and Shih-Yen Lin1, 2*
1Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 2Research Center for Applied Sciences, Academia Sinica, Taiwan.
van der Waals epitaxy of graphene on graphene surfaces is demonstrated by repeating CVD growth cycles directly on sapphire substrates. Improved field-effect mobility values are observed for the bottom-gate transistors fabricated by using the bilayer graphene channel, which indicates that an improved crystallinity is obtained after the second CVD growth cycle. Despite the poor wettability of copper on graphene surfaces, graphene may act as a thin and effective diffusion barrier for copper atoms. The low resistivity values of thin copper films deposited on thin monolayer MoS2/monolayer graphene hetero-structures have demonstrated its potential to replace current thick liner/barrier stacks in back-end interconnects.
Wafer Scale Graphene Nanoribbons with High Mobility through Periodic Phonon Interaction
Teng-Chin Hsu, Bi-Xian Wu, Rong-Teng Lin, Tzu-Hsuan Chang*
Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan
We propose and demonstrate a design of Coved-GNRs with periodic structure ranged from 4 to 14 nm that has band gap opened (0.3eV to 0.1eV) at wafer scale while maintaining high mobility at mass production level. In contrast to unavoidable zero bandgap transition in armchair and zigzag GNRs when edge structures of GNRs varies by only a few atoms, the coved structure can exclude the chances of zero bandgap transitions, and at the same time, reduces electron-phonon scattering in Coved-GNR that making the mobility enhance several orders compared with the zigzag GNRs of same width. We demonstrate the procedures and features of GNRs can be feasibly replicated on the Germanium (110) substrate where the graphene can be prepared in the single-crystal and single-oriented formants and applicable to the current fabrication facility. The edge of the patterned nanoribbons can be further repaired with “balanced condition growth” that is controlled by the process condition.
A record-high mobility of ~ 22 cm2/V-s in a bottom-gate SnS2 field-effect transistor by a pre-pattern process
Rui-Jun Wu1, Shih-Chieh Su2, Hsiang-Shun Kao1, and Jiun-Yun Li1,3,4,5*
1Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 2Graduate Institute of Photonics and Optoelectronics, National Taiwan University, Taiwan, 3Department of Electrical Engineering, National Taiwan University, Taiwan, 4Graduate School of Advanced Technology, National Taiwan University, Taiwan, 5Taiwan Semiconductor Research Institute, Taiwan
Tin disulfide (SnS2) shows great promise for optoelectronics applications owing to its large band gap energy of 2 ~ 2.6 eV than other 2D materials. However, the low mobility (< 10 cm2 /V-s) suggests the poor quality of SnS2. In this works, we demonstrate a recorded-high mobility of ~ 22 cm2 /V-s in a bottom-gate SnS2 field-effect transistor (FET) at 100 K by a pre-pattern process. We find that the ambience has significant effects on carrier transport and the threshold voltage in SnS2 FETs. By placing the SnS2 films into ambience filled with nitrogen, the device performance can be recovered.
Growth of (0001)-textured bismuth nanofilm on SiO2 by MBE
Chieh Chou1, Chia-Hsuan Wu1, and Hao-Hsiung Lin1, 2*
1Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan, 2Department of Electrical Engineering, National Taiwan University, Taiwan
We report on the MBE growth of (0001)-textured bismuth on SiO2 substrate. From XRD and AFM results, we observed the transition from Bi islands to continuous Bi films. The growth is along  direction but with in-plane disorder. The degree of the in-plane disorder is affected by both oxide thickness and Bi film thickness. The grain size reaches 200 nm for 30 nm Bi films, and the roughness is around 1.5 nm.
Role of Crown Ether in Perovskite Precursor for Doctor-bladed Perovskite Solar Cells: Investigated by Liquid-phase Scanning Electron Microscopy
Ming-Hsien Li1*, Kuo-Wei Huang2, Po-Tsung Hsieh3, Chen-Fu Lin2, Raja Rajendran2, Yung-Liang Tung4, and Peter Chen2,3,5*
1Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, Taiwan, 2Department of Photonics, National Cheng Kung University, Taiwan, 3Core Facility Center (CFC), National Cheng Kung University, Taiwan, 4Photovoltaic Technology Division, Green Energy & Environment Research Laboratories, Industrial Technology Research Institute, Taiwan, 5Hierarchical Green-Energy Materials (Hi-GEM) Research Center, National Cheng Kung University, Taiwan
Deposition of large-area perovskite film for perovskite solar cells (PSCs) under ambient process is highly required for their commercial application. In this study, we fabricate mixed-cation and mixed-halide perovskite films by the doctor-blade coating with nontoxic solvent system under ambient process (relative humidity of 40-45%). A crystallization control agent of 18-crown-6 (18C6) is further added in the multiple-component perovskite to improve the film quality. The liquid-phase scanning electron microscopy (L-SEM) is conducted to investigate the effect of 18C6on the perovskite precursor and the doctor-bladed perovskite film. The L-SEM image of pristine perovskite precursor reveals self-assembly micelles, while the additive of 18c6 effectively suppresses the size of perovskite-based micelles in the perovskite precursor. Strong coordination between 18C6and metal cations (such as Cs+ and Pb2+) prevents the perovskite-based micelles from segregation, reducing the micellar size from μm level (without 18C6) to sub-μm level (with 18C6). This effect could result in uniform-sized micelles in the precursor and a reduced crystal growth rate to achieve a high-quality perovskite film with preferred crystallinity, enhanced domain size and large grain size, and smooth surface. The agent of 18c6 in perovskite significantly improves the power conversion efficiency (PCE) of PSCs from 7.8% (without 18C6) to 14.7% (with 18C6).
Strong coupling systems composed of a few fluorophores and a plasmonic nanocavity on designated locations for the foundation of single photon sources
Wan-Ping Chan1*, Jyun-Hong Chen1, Wei-Lun Chou1, Wen-Yuan Chen1, Hao-Yu Liu1, HsiaoChing Hu2, Chien-Chung Jeng2, Jie-Ren Li3, Chi Chen4, and Shiuan-Yeh Chen1
1Department of Photonics, National Cheng Kung University, Taiwan, 2Department of Physics, National Chung Hsing University, Taiwan, 3Department of Chemistry, National Cheng Kung University, Taiwan, 4Research Center for Applied Science, Academia Sinica, Taiwan
Strong coupling systems composed of an atom and a cavity has been utilized for quantum photonic devices. However, it is hardly integrated into a microchip because the alignment between an atom and a cavity needs atom trapping and high vacuum equipment. Here, through DNA strands, a strong coupling unit is constructed by a particle-on-film plasmonic nanocavity and a few fluorophores (Cy5) at ambient conditions. High cavity yield and fluorophore coupling yield are demonstrated. Furthermore, this method is then combined with e-beam lithography to further position a strong coupling unit on a specific location of a microchip.
Fabrication of Indium Oxide Nanoribbon Thin-Film Transistors by Solution-Processing and Low-Temperature Annealing
Zih-Wei Ye1, Wen-Ting Wang1, Hsuan-Jui Ou1, Henry J. H. Chen*1, and Sun-Zen Chen2
1*Department of Electrical Engineering, National Chi Nan University, Taiwan, 2CNMM, National Tsing Hua University, Taiwan
This work focuses on characteristics of the indium oxide (In2O3) nanoribbon thin-film transistors (TFTs), fabricated by solution-processing and low temperature annealing. The In2O3 nanoribbon TFTs showed well output drain current, ON/OFF current ratio, and field-effect mobility with proposed sol-gel process and proper annealing conditions. This process will be suitable for the future 3D-ICs and sensor applications.
Important information for IEDMS2022 accepted Authors:
For Oral Papers:
- The allotted time for oral presentation is 25 minutes for invited speakers and 12 minutes (including presentation and question) for regular oral speakers.
- Check the date, session and presentation time of your papers listed in the website of Preliminary Technical Program.
- Please upload your Letter of Authorization in PDF and presentation file in PDF (for backup use only) to the website of submission.
- Please report to the Session Chair in the session room at least 20 minutes before the session begins.
For accepted Poster Presentation:
- The usable space of the display boards is A1 size.
- Posters should be readable by viewers from up to 1 meter away.
- The paper ID number of each poster and of its corresponding poster board is given in the appropriate session program. Please be sure to set-up your poster on the appropriate poster board 30 minutes before the session begins.
- Please upload your Letter of Authorization in PDF to the website of submission
- Please dismantle your poster right after the session.
Registration for the Conference
- At least one author of the accepted paper must register for the conference by 22 October 2022 12:00pm (EST), otherwise the paper will be withdrawn.
- For non-student authors presenting multiple papers, one FULL or LIMITED registration is valid for up to two
- Please be reminded to complete registration process as soon as possible, the deadline of registration is on 22 October 2022. Early Bird Registration is offered until 11 October 2022.
Best Paper Awards will be announced at Closing Remark on 28 October.
National Chi Nan University
International Electron Devices & Materials Symposium 2022, IEDMS2022
October 27-28, 2022
Welcome to IEDMS 2022!
The 27th International Electron Devices and Materials Symposium (IEDMS 2022) will be held at National Chi Nan University, Puli, Nantou, Taiwan, from Oct. 27 to Oct. 28, 2022. This symposium is one of the prestigious conferences in semiconductor materials and devices, which were held successfully every year in Taiwan since more than decades ago. This year, the IEDMS will be hosted by National Chi Nan University and sponsored by The Electronics Devices and Materials Association, Ministry of Science and Technology Taiwan, and Taiwan Semiconductor Research Institute. This conference offers a platform for international scientists, engineers, and researchers to present the latest research results, ideas, developments, and applications in electron devices and materials.
The Technical Program Committee is inviting papers related, but not limited to, the following areas:
Symposium A: Compound Semiconductor Materials and Devices
Symposium B: Si-Based Processing, Devices and Integration
Symposium C: Novel Materials, Medical device, Battery, Large-Area Electronics, and Related Applications
Symposium D: Photonic Materials/Devices, Novel Device Concept and Applications
Abstract Submission Start : Jun. 20th, 2022 Abstract Submission Deadline : Aug. 10th , 2022 Aug. 25th, 2022 Final Submission Deadline : Sep. 2th, 2022
Notification of Acceptance :
Oct. 1, 2022
Early-Bird Registration Deadline :
Oct. 11th, 2022
- Applied sciences : Special Issue “Selected Papers from ISET 2021, TSBME 2021, ISPE 2021, SEMBA 2022, and IEDMS 2022”
- Membranes : Special Issue ““Semiconductor Membranes” for International Electron Devices & Materials Symposium 2022, IEDMS2022”Special Issue “
- Chemosensors (IF 4.229): Special Issue “Selected Papers from the International Electron Devices and Materials Symposium 2022 (IEDMS 2022)”
- Crystals: Special Issue “Nano-Semiconductors: Devices and Technology”